1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device and an electric device with the same, especially to a data read scheme for a NAND type flash memory which has miniaturized cells.
2. Description of Related Art
Currently known EEPROMs are formed to have a type of memory cell which stores charge in a floating gate thereof. In a NAND type flash memory, which is one of these EEPROMs, data rewriting operation is performed by using FN tunneling current in both of write and read operations. Recently, multi-value storing techniques are going to be introduced so as to store two bits in a memory cell, whereby it becomes possible to increase the memory capacity to be twice without changing the memory cell size.
However, the more miniaturized the NAND type flash memory is, the stronger the interference between the adjacent memory cells becomes, as a result of that the distance between cells becomes small (refer to, for example, Published Unexamined Japanese Patent Application No. 2001-267537). This can be said because that scaling in a vertical direction of the cell array is more difficult than that in a lateral direction.
More specifically, referring to FIG. 20, the interference between the adjacent cells will be described. FIG. 20 shows adjacent three memory cells MC0–MC2 in a NAND cell unit. Giving attention to the memory cell MC1, the floating gate FG1 is capacitively coupled with the control gate (i.e., word line) and the substrate (i.e. channel) by capacitances Cfgwl, Cfgch, respectively. If cells are miniaturized, the capacitance Cfgfg between the floating gates FG1 and FG0 (or FG2) in the adjacent cells MC0 (or MC2) will be relatively increased in comparison with the capacitance Cfgwl or Cfgch. The capacitive coupling between the adjacent floating gates harmfully influence the data read operation.
In detail, assume that after data having been written into the memory cell MC1, data write into the memory cell MC2 is performed. In this case, when data write is performed into the memory cell MC1, the floating gate FG2 of the adjacent memory cell MC2 is held at a first potential. The floating gate FG2 becomes thereafter to be at a second potential as a result of the data writing into the memory cell MC2. Since the data read operation of the memory cell MC1 is influenced by the potential of the floating gate FG2 of the adjacent memory cell MC2, the threshold voltage of the cell MC1 will be changed before and after the writing of the memory cell MC2.
The influence for the above-described threshold voltage will be explained in detail, referring to FIGS. 21 and 22. FIG. 21 shows a NAND cell unit with four memory cells MC0–MC3. One end of the NAND cell unit is connected to source line CELSRC through a select transistor S1, and the other end to bit line BL through another select transistor S2. With respect to this NAND cell unit, it is assumed that data write is performed in order from the memory cell MC0 at the source line CELSRC side toward memory cell MC3 at the bit line BL side. To-be-written data is, for example, four-value data “00”, “01”, “10” or “11” as been expressed by 2-bit/1-cell that have threshold distributions as shown in FIG. 22.
It is noted that the memory cells MC0–MC3 are initialized at an erase state (data “11” state) with the lowest threshold before data writing. As shown in FIG. 21, data write from the erase state into a data state with threshold voltage Va (for example, data “00” shown in FIG. 21) is sequentially performed from the memory cell MC0 at the source line CELSRC side toward the memory cell MC3 at the bit line BL side. Write into the cell MC0, and the threshold becomes Va. When the next cell MC1 is written to have threshold Va, the threshold of the cell MC0 will be shifted from Va to Vb. Since write operation is done by use of electron injection into the floating gate, the potential of the floating gate is shifted in the negative direction by data writing. This potential shift of the floating gate affects the adjacent cell so as to increase the threshold voltage. In other words, as a result of that the potential of the adjacent cell's floating gate is shifted in the negative direction, the threshold of the memory cell under notice becomes higher. As similar to the above-described case, as the memory cell MC2 has be written after writing of the cell MC1, the threshold of the cell MC1 is shifted from Va to Vb. After written into the cell MC3, the threshold of the cell MC2 is shifted from Va to Vb. The threshold of the cell MC3 will be held at Va without being shifted because adjacent device thereof is the select transistor S2 without threshold variation.
In the example of FIG. 21, it has been explained for a case that all cells are sequentially written into the same data state. In a practical data write operation, data writing which affects to shift the threshold of the adjacent cell is not performed in some cases. Therefore, giving attention to, for example, the data “00” shown in FIG. 22, although the threshold distribution width is Vtw1 as far as there are no influences from the adjacent cell, it is widened to be Vtw2 by the influence from the adjacent cell.
In FIG. 22, threshold distributions are shown with respect to two cases: one case in which the influence from the adjacent cell is large; and the other case in which the influence is small. If the influence from the adjacent cell becomes large, some problems occur as follows. First, if the respective threshold distributions are widened due to the influence from the adjacent cell, it becomes necessary for widening the spaces between the respective threshold distributions in order to be sure to execute the precise data read operation of the written data. To do this, it is further required to increase the respective to-be-written thresholds. As a result, a difference between the lowest threshold (i.e., erase state) and the highest written threshold becomes large, thereby leading to a vicious cycle that potential variations of the adjacent cells become large, thereby further widening the respective threshold distributions. Second, a read-use pass voltage Vread, which is applied to non-selected word lines to turn on the non-selected cells, becomes high. This causes data read trouble.
To suppress the above-described interference between the cells, it will be a practical measure that data write is performed in such a manner as to make the respective data threshold distributions as narrow as possible. However, this results in that it takes a long time to write data into the NAND type flash memory. In detail, data writing of the NAND type flash memory is performed by write pulse applications and verify-reads thereafter which are periodically performed with stepping up the write pulse voltages little by little. The above-described scheme is used in consideration of the variation of the write characteristic. To make the threshold distribution narrow, it is necessary to make the step up of the write pulse voltage small. This results in that number of the write cycles is increased, and then write period becomes long.
As above described, as the miniaturization of the cells in the NAND type flash memory is progressed, it becomes a problem that interference between cells becomes large, whereby variation of written data threshold becomes large due to capacitive coupling between the floating gates.